X312P-48Y-T

P4-programmable 25Gb switch with 3.3 Tbps Intel Tofino ASIC and 2x Marvell Octeon TX CN9670 DPUs

4-6 Weeks’ Lead Time for X312P-48Y-T

  • Debian based environment for development quick start
  • SONiC and P4runtime Support Ready
Clear

X312P-48Y-T is an advancing P4 Programmable switch with 3.3Tbps capacity which designed to combine a multi-core X86-based control plane, a programmable barefoot tofino ASIC based data forwarding plane and two high-performance Marvell Octeon TX CN9670 based DPU modules to provide extra L4 -L7 in-depth data processing capability.

48 x 25Gb SFP28, with 12 x 100Gbb QSFP28
Dual-redundant, load-sharing, hot-swappable PSUs
4+1 redundant, hot-swappable fan modules

Asterfusion X312P-48Y-T:

48 ports 25GB with 12 ports 100G uplinks Intel Tofino P4 -programmable switch

After installing software, the X312P-48Y-T can be deployed as a top-of-rack (ToR) switch as well as smart gateway for tasks such as traffic management, load balance, and security processing, with its ASIC level programmability enabling flexibility in dealing with different network scenarios.

Hardware Architecture of X312P-48Y-T Barefoot Tofino Switch

Data Processing Unit Module (Optional)

When employed with more complex applications, such as those which need deep buffer, stateful processing, or L7 processing, the pluggable DPU module can be chosen to provide high performance software data processing, where the DPDK and VPP framework can be used to provide developers a quick start development environment in a similar way to the Intel X86.

  • Marvell Octeon DPU: 24-core ARM64 CN9670 1.8GHz
  • Memory: 3xDDR4 SO-DIMM, up to 96GB
  • Storage:
    • 32GB eMMC5.1 for OS or system software
    • 2xM.2 NVME SSD, up to 2T data storage
    • 2x100G Ethernet interface connecting to Tofino switch
  • Maximum 2x Data Processing Module in the system

When P4 meets DPU (Barefoot Tofino meets Marvell Octeon )

The combination of the T-bit level fast path for high performance wire-speed forwarding and the slow path of in-depth data processing, achieves in-depth service processing and application offloading.

Distributed INT-driven intelligence network optimization, providing local real- time network telemetry information, improving the overall user experience of the application system.

NFV gateways, state-based load balancing and network address translation, reducing the burden of data centers.

Large /small flow separation, it can both meet the high bandwidth of large flow and high concurrency of small flow.

Software Choices of Barefoot Tofino P4 Programmable Switch

AsterNOS

Enterprise NOS based on SONiC
By default,  we provide an enterprise distribution SONiC NOS with feature enhancement and quality assurance with complete code review and system testing. 

AsterNOS-Framework

P4 application development environment
The AsterNOS Framework integrates P4Runtime into a reduced-SONiC version in a docker containers, thus developers can combine powerful management and control planes.

SONiC

Community version
The community version of SONiC can be installed with the pre-loaded ONIE.

What’s in the box

  • RJ45 Console Cable
  • 1RU Switch Hardware
  • 2 Marvell Octeon DPU Extension Cards (Optional)

Tech Specs

Weight

10.1 kg

Dimensions

440 × 525 × 44 mm

Switch Chip

Intel's Tofino

Switch Capacity

3.3T, 48 x 25Gb SFP28, with 12 x 100Gb QSFP28

Control CPU

Intel Broadwell 1508, Intel Broadwell 1527

Physical Dimension

19" 1RU

Thermal Airflow

Port-to-Power, Power-to-Port

Special Discount for Academia and Research program

This model is a part of Asterfusion ‘s P4 programmable switch for Academia and Research program. Please email to us for discounted price before ordering.

Warranty

The Asterfusion® X312P-48Y-T switch is backed by a 2 year limited hardware warranty. Multiple extended support options, including advanced replacement and 24×7 support services, are available. Contact us for complete details.

Warranty

The Asterfusion Helium EC2004  is backed by a 2 year limited hardware warranty. Multiple extended support options, including advanced replacement and 24×7 support services, are available. Contact us for complete details.

Frequently Asked Questions About 312P-48Y-T P4 programmable switch

What is the difference of X312 from Asterfusion versus other vendors with the similar ports?Is it using a different chipset Tofino X or 2?

Asterfusion X312 do have some differences in the system design: 1. We provide 48x25G with 12x100G in 1RU in front panel, 2. We provide 2x DPU extension slots in the same 1RU box with around 600w more power and thermal budget.  These two-system design provides unique features and more design complexity.

Data Processing Unit Module, is it possible to buy separately?

 This DPU module will need a carry board, We usually use DPU module in several of our own switch devices. Well, because this DPU module use our own interfaces, so it cannot be plugged easily to other system unless you develop you own carrier board. If you just want a card can be plugged  into server, your use our DPU based SmartNIC

What’s your software support for Barefoot Tofino switch?

For software support: we will offer you patch for BSP of platform for the SDE; if you want to develop a switch like application, you can use SONiC from the community and we will offer you patches to support hardware.

How many packets can fit into a single queue – i.e. what is the buffer size? and do you have any performance penalty when using hQoS?

In theory, there is no limitations on packet number in a queue, but all the queues share 20MB memory. There is no performance penalty in the scheduler because it’s a part of ASIC

How do you handle hQoS on your tofino switch , is there any support for it?

The tofino chip supports a single level scheduler with some added flexibility. Overall, the scheduler provides the following capabilities:

  • Strict Priority and Weighted Round Robin (WRR) scheduling between queues
  • Minimum bandwidth guarantees per queue on a byte or packet basis
  • Maximum bandwidth shaping per queue on a byte or packet basis
  • Maximum bandwidth shaping per port on a byte or packet basis

Please tell us whether the development environment SDK or BSP will be provided for us if we want to develop our own software to run on your tofino X-T series?

If you want develop application for P4 data plane, then the SDE from intel would help you, we will offer you patch for BSP of platform for the SDE;  if you want to develop a switch like application, you can use SONiC from community and we will offer you patches to support our hardware; We can even help you to combine P4 and SONiC together to reduce you time-to-market. We have a 30+ people team working on P4 related work and rich experience to develop varies network traffic processing applications on Tofino.

For the Tofino X-T series , please provide a list of what you supported ?Do you offer special discount for academia and research program?

In the hardware bare metal, there are two options: 1. ONIE; 2. ONIE with ONL or Debian

Yes, For tofino series switch, Asterfusion offers 10% off  for academia and research program. Please email to [email protected] to consult.

What is the cost to have the SDK license from Intel?

It depends on what kind of application are you developing, usually people can start from SONiC community version for switch enhancement, we can offer you a ready-to-run SONiC version as your development basis; or people need to develop some new applications like NPB or gateway using P4, at this time you will have get a license from Intel, usually it is a huge project when you start your development, lets discuss in the meeting to see how we can help.

We are looking into P4 for our vBNG and would like to purchase a switch for our development efforts – your model X312P-48Y-T seems good, but can you tell us how much memory is available for forwarding purposes? Memory is critical for use due to the nature of the vBNG.

When talking about memory I think you must be familiar with Tofino chip, there is only internal buffer memory onchip, which is 20MB. But I also guess you may ask the memory on the daughter card connecting to the Tofino, which is a 24-core ARM64 DPU based H/W and you can write and run vNF code in the DPU.

Just to get things clear, this is 20MB per whole switch or per port?I don’t know actually how this works when you have a lookup table for a P4 program, e.g. the routing table. Does the routing table use only the on-chip memory or can use the ARM64 as well?

20MB for whole chip and shared by all ports. When we implement our own vNF, we use DPU card to process all traffic while offload elephant flow to Tofino program written in P4.Which means, on chip memory and on chip table usually used as a fast flow cache for vNF programs on DPU.

I need to clarify some aspects such as the SONiC environment, the way to interact with it, and specially how we could take advantage of the switch through P4 programming.

  • Since you want to start to explore P4 programming, I think it will be a good start to get a copy of SDE from intel, there are several components inside the SDE.
  • There is a data plane implementation using P4 called switch.p4, it’s a L2/L3 switch reference design you can use in your project, usually you can modify the design to make it suitable for your requirement and also you can use it directly in most cases.
  • Then you can access SONiC community on github, you can build SONiC by the instruction from site, we will provide you BSP patch so that your building image can be used on our H/W.
  • There is a SAI interface in the SONiC, SDE provides the SAI implementation for tofino, that is the connection between SONiC and SDE, if you would like, you can read code of both SAI interface and SAI implementation.

Do you know by chance if SDE licenses can be requested for academy and research?

  • SDE is not a software switch implementation, it’s the official development of tofino switch ASIC
  • There is a switch.p4 source code in the SDE, of course, some other tools like P4 compiler and a lot of libraries, the switch.p4 can run on the simulator, but it will be better to run the objective code of switch.p4 on the hardware .now the SDE officially calls p4-studio.
  • For Broadcom or Marvell switch, ASIC vendors implement packet processing pipeline, but for tofino, it is the swith. p4 implements the pipeline, so you can modify the pipeline in your project.
  • SDE offers data plane implementation & control plane access interfaces; SONiC will call control plane access interfaces to build forwarding tables for data plane.
  • When you get SDE and SONiC, you can do all the work virtually as you described above (but we don’t recommend so, because the simulation has quite some limitations). We will provide you BSP to patch the SDE and SONiC, then you can build real image to run on our hardware.

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Asterfusion Data Technologies Co., Ltd.

Floor 4, Building A2, Shahutiandi, No.192 Tinglan Road, SIP

23F - E08, Dinghe Tower, Jintian Road, Futian, Shenzhen

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