4-6 Weeks’ Lead Time for X312P-48Y-T
X312P-48Y-T is an advancing P4 Programmable switch with 3.3Tbps capacity which designed to combine a multi-core X86-based control plane, a programmable barefoot tofino ASIC based data forwarding plane and two high-performance Marvell Octeon TX CN9670 based DPU modules to provide extra L4 -L7 in-depth data processing capability.
48 x 25Gb SFP28, with 12 x 100Gb QSFP28
Dual-redundant, load-sharing, hot-swappable PSUs
4+1 redundant, hot-swappable fan modules
The combination of the T-bit level fast path for high performance wire-speed forwarding and the slow path of in-depth data processing, achieves in-depth service processing and application offloading.
Distributed INT-driven intelligence network optimization, providing local real- time network telemetry information, improving the overall user experience of the application system.
NFV gateways, state-based load balancing and network address translation, reducing the burden of data centers.
Large /small flow separation, it can both meet the high bandwidth of large flow and high concurrency of small flow.
This model is a part of Asterfusion ‘s P4 programmable switch for Academia and Research program. Please email to us for discounted price before ordering.
Asterfusion X312 do have some differences in the system design: 1. We provide 48x25G with 12x100G in 1RU in front panel, 2. We provide 2x DPU extension slots in the same 1RU box with around 600w more power and thermal budget. These two-system design provides unique features and more design complexity.
This DPU module will need a carry board, We usually use DPU module in several of our own switch devices. Well, because this DPU module use our own interfaces, so it cannot be plugged easily to other system unless you develop you own carrier board. If you just want a card can be plugged into server, your use our DPU based SmartNIC
For software support: we will offer you patch for BSP of platform for the SDE; if you want to develop a switch like application, you can use SONiC from the community and we will offer you patches to support hardware.
In theory, there is no limitations on packet number in a queue, but all the queues share 20MB memory. There is no performance penalty in the scheduler because it’s a part of ASIC
The tofino chip supports a single level scheduler with some added flexibility. Overall, the scheduler provides the following capabilities:
If you want develop application for P4 data plane, then the SDE from intel would help you, we will offer you patch for BSP of platform for the SDE; if you want to develop a switch like application, you can use SONiC from community and we will offer you patches to support our hardware; We can even help you to combine P4 and SONiC together to reduce you time-to-market. We have a 30+ people team working on P4 related work and rich experience to develop varies network traffic processing applications on Tofino.
In the hardware bare metal, there are two options: 1. ONIE; 2. ONIE with ONL or Debian
Yes, For tofino series switch, Asterfusion offers 10% off for academia and research program. Please email to [email protected] to consult.
It depends on what kind of application are you developing, usually people can start from SONiC community version for switch enhancement, we can offer you a ready-to-run SONiC version as your development basis; or people need to develop some new applications like NPB or gateway using P4, at this time you will have get a license from Intel, usually it is a huge project when you start your development, let’s discuss in the meeting to see how we can help.
When talking about memory I think you must be familiar with Tofino chip, there is only internal buffer memory onchip, which is 20MB. But I also guess you may ask the memory on the daughter card connecting to the Tofino, which is a 24-core ARM64 DPU based H/W and you can write and run vNF code in the DPU.
20MB for whole chip and shared by all ports. When we implement our own vNF, we use DPU card to process all traffic while offload elephant flow to Tofino program written in P4.Which means, on chip memory and on chip table usually used as a fast flow cache for vNF programs on DPU.
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