How to Choose between Marvell Octeon CN103 and CN9670 for Advanced Packet Broker Features?

Introduction

In Network Packet Broker (NPB) scenarios, the choice of DPU directly impacts power consumption, processing efficiency, and product lifecycle.

All packet broker platforms in our portfolio are built on Marvell DPU families. This article focuses on two mainstream options: OCTEON TX2 CN9670 and OCTEON 10 CN10308. Learn with us how to choose between Marvell Octeon CN103 and CN9670.

It analyzes their suitability based on deployment requirements. The goal is to provide practical guidance for DPU selection in 100G NPB deployments.

For NPB solutions, refer to Network Packet Broker Powered by SONiC: PB-APP Solution

Ⅰ. Why 100G is the Upper Limit in NPB Scenarios

Before learning how to choose between Marvell Octeon CN103 and CN9670, it is necessary to define the key constraints and requirements of the target scenario. This provides the baseline for selection.

1. Root Causes of the 100G Bandwidth Limit

The 100G ceiling is defined by both hardware architecture and DPU capability.

On the hardware side, the CX306P-48Y-M-H switch ASIC imposes a fixed internal topology. The interconnect bandwidth between the DPU and the switch is limited to 100G. This is a hard limit and cannot be exceeded.

On the DPU side, current processing capacity aligns with 100G line rate. Higher bandwidth, such as 200G, does not provide practical benefit in this scenario.

Traffic sent to the DPU is pre-filtered by the switch ASIC. It is used for advanced processing in FusionNOS, such as deep packet filtering and data masking.

At 100G, the system achieves a balanced match across hardware capability, processing efficiency, and service requirements.

Note: Fusion is a NOS for the DPU platform that supports both standard packet broker and advanced functions.

2. Key Design Requirements for 100G NPB Deployments

• Bandwidth: Sustained 100G line-rate operation. No packet loss. Low latency. Must align with the CX306P-48Y-M-H and DPU interconnect design.
• Core capabilities: The switch ASIC handles baseline NPB forwarding. The DPU offloads advanced FusionNOS functions. Hardware specifications must be considered, including accelerators and memory. Accelerators mainly impact CRC processing and compression performance.
• Deployment and lifecycle: Power efficiency and cost control are required. Long-term supply must be ensured. The platform should allow moderate scalability. It must avoid selection risks tied to hardware obsolescence. Compatibility with existing deployments and support for new rollouts are both required.

Ⅱ. Key Parameter Comparison between Marvell Octeon CN103 and CN9670

Exclude non-critical specifications. Focus on parameters that directly impact selection decisions.

Highlight the differences in scenario fit between the two chipsets.

Dimension (Hardware View)	Marvell CN10308 (GHC103 Module)	Marvell CN9670 (GHC96 Module)	Impact in 100G NPB Scenarios (Objective)
Process Node	5nm (TSMC)	16nm	CN10308 uses a more advanced node. Higher energy efficiency. Lower thermal output. Easier thermal design. CN9670 uses an older node. Lower efficiency. Higher heat. Stricter cooling requirements.
CPU Configuration	8-core Arm Neoverse N2 (v9), 2.5 GHz	24-core Arm v8.2 (custom OCTEON TX2), 1.8 GHz	CN10308’s per-core IPC is three times CN9130’s, and VPP accelerators boost packet processing over fivefold, giving lower single-core latency. CN9670 has more cores but lower frequency, limiting per-core efficiency.
Typical Module Power	~40W	~80W	CN10308 consumes significantly less power. Lower cooling demand. Reduced long-term OPEX. CN9670 has higher power draw. Higher thermal pressure. Requires stronger cooling design. Higher OPEX.
Memory Slots	2× DDR5, up to 48 GB	3× DDR4, up to 96 GB	CN10308 uses DDR5 with higher bandwidth. Capacity up to 48 GB. CN9670 supports DDR4. Higher maximum capacity at 96 GB.
Switch Interconnect	100G	100G	Limited by CX306P-48Y-M-H to 100G. No practical difference. Both meet line-rate requirements. No impact on NPB forwarding or FusionNOS processing.
Lifecycle	Current generation. Long-term supply. Active roadmap. Timely software updates and fixes	Previous generation. Gradual phase-out. Limited future updates. Spare parts availability will decline	CN10308 is suitable for new deployments. Lower lifecycle risk. Better long-term support. CN9670 has limited future support. Higher operational risk. Suitable for short-term or legacy compatibility scenarios.
Forwarding Performance (100G)	Line-rate. No bottleneck. Lower latency	Line-rate. No bottleneck. Slightly higher latency	Both meet 100G requirements. CN9670 shows slightly higher latency due to lower core efficiency and higher power profile.
Hardware Compatibility	Fully compatible with CX306P-48Y-M-H. Supports FusionNOS	Fully compatible with CX306P-48Y-M-H. Supports FusionNOS	No compatibility differences.
Storage	64GB eMMC. Optional NVMe	64GB eMMC. Optional NVMe	No difference.
Additional Features	Integrated ML/AI acceleration engine	None	CN10308 supports hardware ML/AI acceleration. Can be used for anomaly detection, intelligent QoS, and threat identification. Not available on CN9670.

Ⅲ. Root Causes of Differences between Marvell Octeon CN103 and CN9670

The power gap between the two chips (CN9670 ~80W+, CN10308 ~40W) is driven by architectural differences.

1. Primary Factors: Process Node and CPU Architecture

• Process node: CN10308 uses a 5nm process. Lower leakage. Higher energy efficiency. Lower base power. CN9670 is built on 16nm. Higher leakage. Lower efficiency. Higher baseline power.
• CPU architecture: FusionNOS relies on a global hash mechanism. CN10308 uses an 8-core Arm v9 architecture. High per-core efficiency. Lower lock contention. CN9670 uses 24 cores on Arm v8.2. Lower per-core efficiency. Higher multi-core coordination overhead. This increases power consumption.

2. Secondary Factors: I/O and Acceleration Blocks

CN10308 integrates 50G SerDes, DDR5, and more efficient hardware accelerators. These improve processing efficiency and reduce power per workload.

CN9670 uses older I/O and acceleration designs. Lower efficiency. Additional power overhead during processing.

Ⅳ. Key Reasons to Prefer CN10308

• Higher efficiency: At 100G line rate, CN10308’s high per-core performance avoids multi-core lock contention. Core utilization is much higher than CN9670. FusionNOS processes workloads more efficiently.
• Lower power consumption: The 5nm process reduces CN10308 power to roughly 50% of CN9670, lowering long-term operational costs.
• Better memory performance: Supports DDR5 with higher frequency and bandwidth.
• Expanded ML/AI acceleration: Hardware engine enables future functions such as traffic anomaly detection, intelligent QoS, and security threat identification.

Ⅴ. Selection Conclusion and Recommendations

Based on the above, while we recommend CN10308 as the first choice, CN9670 is not entirely obsolete in other scenarios.

The following outlines the selection criteria to help determine which DPU best fits your specific needs.

1. Prefer CN10308 (First Choice for New Projects)

Recommended for new 100G NPB designs. Suitable for users who:

1. Require low power and thermal footprint to reduce long-term OPEX and cooling investment.
2. Do not rely on accelerators for CRC or compression, with modest memory expansion needs.
3. Prioritize advanced technology, stable long-term supply, and lifecycle risk mitigation.
4. Demand high FusionNOS processing efficiency, with strict single-core performance and low forwarding latency.
5. Plan for future expansion. The ML/AI acceleration engine supports traffic anomaly detection, intelligent QoS, and threat detection—capabilities not available on CN9670.

2. Optional/Retain CN9670 (Scenario-Specific)

Applicable in specific cases:

1. Workloads depend on the co-processor (e.g., CRC or compression).
2. High memory capacity is required for large deployments.
3. Upgrading legacy projects that must remain compatible with existing hardware/software. No power optimization required and no additional redesign cost is acceptable.
4. Short-term deployments with no immediate upgrade plans. Higher power consumption and limited future support are acceptable.

Ⅵ. Avoiding Selection Misconceptions: Q&A

Misconception 1: More cores equal better performance ?

At 100G, CN9670’s 24 cores have low per-core efficiency and high lock contention. Core utilization is low, increasing power consumption. Single-core performance is the critical factor.

Misconception 2: Older platforms are more stable ?

CN10308, as a next-generation platform, matches CN9670 in stability. It also offers better supply continuity and expansion potential.

Misconception 3: NPB and FusionNOS are the same system ?

They operate at different layers. NPB handles baseline forwarding on the switch ASIC running AsterNOS. FusionNOS runs on the DPU for advanced processing. Each has distinct responsibilities.

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