CX204P-16Y-M-E
16x25Gb SFP28, 4x100Gb QSFP28 L3 Spine/Aggregation Switch, Enterprise SONiC Ready, MLAG VXLAN
16-port 25Gb SFP28 L3 Aggregation Switch, 4x100Gb QSFP28 Uplinks, Enterprise SONiC NOS, Marvell Aldrin 2
Asterfusion CX204P-16Y-M-E is a 16-port 25G spine switch with 4 ports 100G QSFP28 uplinks, suited for campus aggregation or spine applications, enterprise networks, and cloud service provider network deployments. It is powered by a Marvell Aldrin 2 chip in a compact 1RU form factor. Moreover, this 16-port 25G network switch comes with Enterprise SONiC installed and is ideal for enterprise fabric.
Specifications
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Hardware Panel

Features

Layer 2 Features
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4K VLANs
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Voice VLAN
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Multiple Spanning Tree Protocol (MSTP)
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QinQ
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Link Aggregation Control Protocol (LACP)
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Multi-Chassis Link Aggregation (MC-LAG)
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VLAN Trunking
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Link Layer Discovery Protocol (LLDP)
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LLDP Enhancements for PoE
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Port Isolation
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Jumbo Frames (9216 Bytes)
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Storm Control
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Monitor Link

Layer 3 Features
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IPv4/v6 Dual Stack
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Policy Based Routing
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Resilient ECMP
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ARP-to-Host
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VRF
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Bi-Directional Forwarding Detection (BFD)
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Route Map
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VRRP
- Routing Protocols: OSPF v2/v3, BGP, MP-BGP

Security Features
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Service ACLs
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ACL Logging and Counters
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Control Plane Policing (CoPP)
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DHCPv4/v6 Relay
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DHCPv4/v6 Snooping
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ND Snooping
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TACACS+

Management and Monitoring
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Asteria Campus Controller
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Industry Standard CLI
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Zero Touch Provisioning (ZTP)
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SNMP v1/v2/v3
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Port Mirroring
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Syslog
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Log Management
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PTP IEEE 1588v2 (TC and BC)
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Containerized Custom Tools

Quality of Service (QoS)
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8 Queues per Port
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802.1p Based Classification
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DSCP Based Classification
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Strict priority queueing
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DWRR Scheduling
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Policing/Shaping
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Rate Limiting

Virtualization Features
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VXLAN Centralized/Distributed Gateway
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EVPN Type 2/3/5
Enterprise SONiC 16-port 25Gb Layer2/3 Switches with PTP Support(Optional)
Currently, the CX204P-16Y-M-E layer 2 and layer 3 access switches offer support for the IEEE1588 PTPv2 standard through both hardware and software. The hardware port offers full support for PTP and can be used as boundary clock(BC) or Transparent clock (TC). The module can be flexibly disassembled based on customer requirements.
On the software side, Asterfusion leads the community in implementing the PTP function in SONiC and optimizing its performance on our Enterprise SONiC Distribution –AsterNOS. By utilizing hardware acceleration and software algorithm optimization, the PTP protocol achieves a synchronization deviation of only 10ns, significantly enhancing speed and stability in protocol interaction. Additionally, interoperability is greatly improved as it supports configurations such as restAPI, RestConf, Netconf, and CLI.
