48×25Gb, 8×100Gb P4-programmable switch with 3.3 Tbps Intel Tofino ASIC ,2x Marvell Octeon TX CN9670 DPUs

Asterfusion X308 do have some differences in the system design: 1. We provide 48x25G with 8x100G in 1RU in front panel, 2. We provide 2x DPU extension slots in the same 1RU box with around 600w more power and thermal budget. These two-system design provides unique features and more design complexity.

For software support: we will offer you patch for BSP of platform for the SDE; if you want to develop a switch like application, you can use SONiC from the community and we will offer you patches to support hardware.

The Tofino chip supports a single level scheduler with some added flexibility. Overall, the scheduler provides the following capabilities:

• Strict Priority and Weighted Round Robin (WRR) scheduling between queues
• Minimum bandwidth guarantees per queue on a byte or packet basis
• Maximum bandwidth shaping per queue on a byte or packet basis
• Maximum bandwidth shaping per port on a byte or packet basis

In the hardware bare metal, there are two options: 1. ONIE; 2. ONIE with ONL or Debian

Yes, For tofino series switch, Asterfusion offers 10% off  for academia and research program. Please email us.

When talking about memory I think you must be familiar with Tofino chip, there is only internal buffer memory onchip, which is 20MB. But I also guess you may ask the memory on the daughter card connecting to the Tofino, which is a 24-core ARM64 DPU based H/W and you can write and run vNF code in the DPU.

• Since you want to start to explore P4 programming, I think it will be a good start to get a copy of SDE from intel, there are several components inside the SDE.
• There is a data plane implementation using P4 called switch.p4, it’s a L2/L3 switch reference design you can use in your project, usually you can modify the design to make it suitable for your requirement and also you can use it directly in most cases.
• Then you can access SONiC community on github, you can build SONiC by the instruction from site, we will provide you BSP patch so that your building image can be used on our H/W.
• There is a SAI interface in the SONiC, SDE provides the SAI implementation for tofino, that is the connection between SONiC and SDE, if you would like, you can read code of both SAI interface and SAI implementation.

This DPU module will need a carry board, We usually use DPU module in several of our own switch devices. Well, because this DPU module use our own interfaces, so it cannot be plugged easily to other system unless you develop you own carrier board. If you just want a card can be plugged  into server, your use our DPU based SmartNIC

In theory, there is no limitations on packet number in a queue, but all the queues share 20MB memory. There is no performance penalty in the scheduler because it’s a part of ASIC

If you want develop application for P4 data plane, then the SDE from intel would help you, we will offer you patch for BSP of platform for the SDE; if you want to develop a switch like application, you can use SONiC from community and we will offer you patches to support our hardware; We can even help you to combine P4 and SONiC together to reduce you time-to-market. We have a 30+ people team working on P4 related work and rich experience to develop varies network traffic processing applications on Tofino.

It depends on what kind of application are you developing, usually people can start from SONiC community version for switch enhancement, we can offer you a ready-to-run SONiC version as your development basis; or people need to develop some new applications like NPB or gateway using P4, at this time you will have get a license from Intel, usually it is a huge project when you start your development, let’s discuss in the meeting to see how we can help.

20MB for whole chip and shared by all ports. When we implement our own vNF, we use DPU card to process all traffic while offload elephant flow to Tofino program written in P4.Which means, on chip memory and on chip table usually used as a fast flow cache for vNF programs on DPU.

• SDE is not a software switch implementation, it’s the official development of tofino switch ASIC
• There is a switch.p4 source code in the SDE, of course, some other tools like P4 compiler and a lot of libraries, the switch.p4 can run on the simulator, but it will be better to run the objective code of switch.p4 on the hardware .now the SDE officially calls p4-studio.
• For Broadcom or Marvell switch, ASIC vendors implement packet processing pipeline, but for tofino, it is the swith. p4 implements the pipeline, so you can modify the pipeline in your project.
• SDE offers data plane implementation & control plane access interfaces; SONiC will call control plane access interfaces to build forwarding tables for data plane.
• When you get SDE and SONiC, you can do all the work virtually as you described above (but we don’t recommend so, because the simulation has quite some limitations). We will provide you BSP to patch the SDE and SONiC, then you can build real image to run on our hardware.