Table of Contents
Introduction
In the AI-driven era, network infrastructure is confronting practical challenges. Within artificial intelligence (AI) and machine learning (ML) scenarios, the demand for network bandwidth generated by data interaction keeps growing, while the requirement for latency becomes increasingly stringent — these factors directly drive the upgrade of network architecture from cloud to edge. During this process, the bottleneck of network performance is gradually converging on the technical capabilities of underlying hardware, namely Application-Specific Integrated Circuits (ASICs).
Marvell boasts mature technologies in the field of high-performance network chips, and its Marvell Ethernet Switches-based ASIC solutions serve as a crucial underpinning for addressing current network demands. Looking across Asterfusion’s three major product lines — campus, data center, and edge gateway routers — its self-developed AsterNOS open network operating system forms effective collaboration with the three core chip product lines under Marvell’s open network ASIC architecture. These three chip product lines have clear divisions of labor:
- Prestera (including Falcon, Aldrin2/3, and AlleyCat 5X/5Y) focuses on basic switching functions;
- Teralynx specializes in high-speed switching scenarios;
- OCTEON is responsible for intelligent data processing.
The three work in synergy to support a complete open network system covering the access layer → aggregation layer → core layer → intelligent edge, with Marvell Ethernet Switches acting as the core hardware foundation throughout the system.
Ⅰ. Marvell OCTEON with AsterNOS-VPP for Open Gateway Router & DPU
This section focuses on routers and DPU (Data Processing Unit) platforms, which adopt Marvell’s OCTEON series chips. The OCTEON series is positioned as a high-performance, multi-core, programmable intelligent processing platform, suitable for 5G, cloud computing, enterprise networks, and security/monitoring applications.
- OCTEON 10 (CN102/CN103) – Router
OCTEON 10 (CN102/CN103) is equipped with 8 ARM64 Neoverse N2 cores, supports DDR5 memory expansion, and integrates a dedicated routing acceleration engine. It enables hardware offloading for tasks such as IPv4/IPv6 forwarding and BGP protocol processing, preventing unnecessary CPU resource consumption.
Unlike switching chips, OCTEON 10 does not take high-port-density switching as its primary goal; instead, it focuses on routing. Asterfusion delivers routing capabilities through the “AsterNOS+VPP” architecture — AsterNOS (developed based on SONiC) handles routing protocol configuration and device management in the control plane, while VPP (Vector Packet Processing) runs on ASIC hardware to accelerate packet forwarding in the data plane. With forwarding latency as low as the microsecond level, it enables high-performance, programmable white-box routing.
- OCTEON TX2 (CN9670) – DPU/SmartNIC
OCTEON TX2 (CN9670) provides 24-48 core ARM64 CPUs, integrates PCIe Gen4 interfaces and hardware encryption engines, and supports “non-forwarding intelligent tasks” such as virtualization offloading, security processing, and data compression. Its core purpose is to “reduce the load” on servers — transferring network tasks that were originally handled by the CPU to DPU hardware.Compared with OCTEON 10 (designed for routers), OCTEON TX2 focuses more on “service offloading” rather than routing and forwarding. For example, in cloud computing scenarios, it can offload tasks such as KVM virtualized network I/O, VXLAN tunnel encapsulation/decapsulation, and IPsec encryption to hardware, reducing server CPU utilization.
Ⅱ. Marvell Teralynx & Prestera powering Ultra Scale Data Center
The Asterfusion Data Center (DC) product line is mainly driven by Marvell’s Teralynx series and part of the Prestera (Falcon) series chips, — key components of Marvell Ethernet Switches — which are designed for cloud computing and AI/HPC environments requiring high throughput and low latency.
Teralynx 7 (IVM77500 / IVM77700): Balanced Performance for Data Center Spine Layers
It covers a switching capacity of 3.2-12.8 Tbps, supports 100G/200G/400G ports, and has a stable latency of ~500ns. Asterfusion products support 9216-byte Jumbo Frames, which can reduce the number of packet fragmentations and improve the efficiency of large-file transmission.
Compared with the Prestera series, the core difference of Teralynx 7 lies in “speed and latency” — the 32×400G ports of CX732Q-N support a single-port speed of 400G, which is 4 times that of Prestera Falcon 2.0T (maximum 100G); the ~500ns latency is more than 60% lower than the ~1400ns of Falcon 2.0T, making it more suitable for RDMA traffic forwarding in AI training clusters.
Asterfusion Product Mapping: CX532P-N, CX564P-N, CX664D-N, CX732Q-N
Teralynx 10: Flagship Chip for Next-Gen AI Data Centers
The switching capacity of Teralynx 10 jumps to 51.2 Tbps, supporting multi-rate ports of 800G/400G/200G/100G (a single device supports up to 512×100G ports). The cut-through latency is only 560ns, and it integrates the FASTER architecture (Terabit Ethernet Router Slicing), which can simplify network layers and reduce total cost of ownership (TCO).
As the flagship model of the Teralynx family, its core difference from Teralynx 7 lies in “capacity and forward-looking capabilities” — the 51.2 Tbps switching capacity is 4 times that of Teralynx 7 (12.8 Tbps). The 800G ports support high-speed access for next-generation servers, which can meet the traffic demands of ultra-large-scale AI data centers (such as kilocalorie GPU clusters), solidifying its role as the future infrastructure of Marvell Ethernet Switches for next-generation AI/ML and ultra-large-scale cloud networks.
Prestera (Falcon) 2.0T: Reliable ToR Access for Data Centers
Although the Prestera Falcon (2.0T) chip (used in CX308P-48Y-N-V2) belongs to the Prestera series, it is a key choice for the data center ToR (Top of Rack) access layer. It has a throughput of 2.0 Tbps, a forwarding capacity of 2.8 Bpps, and enhanced IPv4 routing capabilities. It supports more than 48 high-density ports, enabling efficient connectivity between servers, storage, and the core network. It excels at handling east-west traffic at the ToR layer; while its ~1400ns latency is higher than that of Teralynx, it still meets the requirements of most ToR scenarios.
This chip also supports large-scale VRF/VXLAN isolation and is compatible with protocols such as BGP and OSPF for fast route convergence. Even when virtual machines or containers are migrated frequently, it can ensure service continuity, making it suitable for multi-tenant data centers and dynamic business needs. Its compatibility with multi-tenant scenarios also expands the application scope of Marvell Ethernet Switches in medium-to-small data centers.
Asterfusion Product: CX308P-48Y-N-V2
For more comprehensive details, refer to the full article: Powerful Marvell Teralynx and Falcon Chips in Asterfusion Data Center Switches
Ⅲ. Marvell Prestera Series: Enterprise-Grade Access & Aggregation Layer Chips
The Marvell Prestera series is a pillar product of Marvell, a core part of Marvell Ethernet Switches, and serves as the core of “general-purpose switching”. It covers the access layer and aggregation layer of enterprise campuses and medium-to-small data centers. Through sub-series such as AlleyCat, Aldrin, and Falcon, it achieves differentiated adaptation ranging from 1G to 100G speeds, and from simple access to complex aggregation scenarios.
Falcon: “Performance Supplement” for High-End Campuses and Data Center ToR
It has a switching capacity of 2.0-3.2 Tbps, supports 25G/100G ports, and features enhanced IPv4 routing table capacity. It also supports PTP IEEE 1588v2 (some models support time synchronization for O-RAN fronthaul), enabling it to meet the needs of both high-end campus core scenarios and Top of Rack (ToR) scenarios in medium-to-small data centers.
As mentioned earlier, Asterfusion’s data center product CX308P-48Y-N-V2 also adopts this chip, which further reflects the wide range of its application scenarios.
Compared with the Teralynx series, the core difference of Falcon lies in “scenario versatility” — although its switching capacity (2.0 Tbps) is lower than that of Teralynx 7 (3.2 Tbps), it supports IEEE 1588v2 and SyncE required for O-RAN fronthaul, allowing it to adapt to 5G base station fronthaul scenarios in the telecommunications industry; compared with Aldrin, it has higher 25G port density (48×25G), making it more suitable for high-density server access.
For detailed specifications, please refer to Falcon 2.0T (Prestera 98CX85xx)
Prestera Series (Aldrin3/Aldrin2): Flexible Campus Aggregation with 5G Readiness
It supports 10G/25G/100G ports, integrates VXLAN tunnel encapsulation capabilities, and enhances security functions (such as IP Source Guard). Some models (Aldrin3, 98DX7332) support SyncE synchronization, adapting to the “multi-access + security + flexible networking” requirements of the campus aggregation layer.
Compared with AlleyCat, the core difference of Aldrin lies in “networking capability and scalability” — it supports VXLAN, which enables the construction of large Layer 2 virtual networks and realizes cross-regional terminal roaming; it also supports MC-LAG (Multi-Chassis Link Aggregation), which can connect two core switches to avoid single points of failure.
For scenarios requiring 5G fronthaul, latency sensitivity, network slicing, or time synchronization, Prestera Aldrin3 has more advantages, as this product excels in these aspects and explicitly supports Class C synchronization, SyncE, and more; while for campus LAN, access, or relatively traditional enterprise network use cases, Prestera Aldrin2 is sufficient and offers better cost-effectiveness.
Prestera Series(AlleyCat5Y/AlleyCat5X): Cost-Effective Access for Terminal-Dense Scenarios
It focuses on 1G/2.5G/5G/10G multi-rate ports, supports DHCP/ND Snooping security protection, integrates PTP IEEE 1588v1/v2 time synchronization function, features low power consumption and controllable cost, and is suitable for terminal-dense access scenarios.
Compared with Aldrin and Falcon in the same family, the core difference of AlleyCat lies in “speed and function simplification”. It supports a maximum port speed of 10G (Falcon supports 25G/100G); some models (such as CX102S-8GT-M-SWP) do not support VXLAN or BGP-EVPN, but provide basic security functions like DHCP/ND Snooping, with better cost-effectiveness. Therefore, it is more suitable for terminal access rather than core aggregation. Among them, AlleyCat 5X supports 2.5G/5G multi-rate uplinks, while AlleyCat 5Y focuses on 10G/25G uplinks. This cost-efficient design makes AlleyCat a go-to choice for entry-level Marvell Ethernet Switches, perfectly fitting budget-sensitive enterprise access layer needs.
Ⅳ. Marvell Ethernet Switches & Router Comparison: Matching Asterfusion Products to Use Cases
Within the Asterfusion product portfolio, the value of Marvell chips is demonstrated as follows:
- Campus Series (Access/Aggregation Layer): Adopts AlleyCat5X / 5Y / Aldrin2 / Aldrin3— core chips of Marvell Ethernet Switches —to match different bandwidth requirements. It also uses Falcon 2.0T and 3.2T as high-end core/spine switching devices.
- Data Center Series (Core/ToR Layer): Employs Falcon / Teralynx7 / Teralynx10, designed for high throughput and low latency scenarios.
- Router Series: Equipped with Marvell OCTEON DPU (CN102/CN103), responsible for separating control plane and data plane.
- DPU Platform: Utilizes OCTEON TX2 CN9670, adapted to the FusionNOS framework for upper-layer service deployment and function acceleration.
To better illustrate the differences among Marvell’s three chip families, we compare them across four dimensions—core capabilities, speed, latency, and scenarios—with reference to Asterfusion products.
| Chip Family | Core Capabilities | Port Speed Range | Typical Latency | Core Scenarios | Representative Asterfusion Products | Key Functional Differences |
| OCTEON | Intelligent Processing (Routing/DPU) | 10G/100G | Microsecond-level | Routers, Edge DPU | ET2508 (Routing), ET3212A (DPU) | Control + data plane separation; supports routing protocols / service offloading |
| Teralynx | High-Speed Switching | 100G/200G/400G/800G | ~500ns-560ns | AI Data Center Core/Aggregation | CX732Q-N (400G), CX864E-N (800G) | Ultra-high switching capacity (up to 51.2Tbps); low latency; supports Jumbo Frame |
| Prestera-Falcon | High-End Campus/DC ToR | 25G/100G | ~1400ns | Campus Core, DC ToR, O-RAN Fronthaul | CX308P-48Y-N-V2, CX306P-48Y-M-H | High port density; supports O-RAN time synchronization |
| Prestera-Aldrin | Campus Aggregation | 10G/25G/100G | Microsecond-level | Campus Aggregation Layer | CX202P-24Y-M-H, CX206P-48S-M-H | Supports VXLAN/EVPN and MC-LAG; enhanced security features |
| Prestera-AlleyCat | General-Purpose Access | 1G/2.5G/5G/10G | Microsecond-level | Campus Access Layer | CX102S-8MT-M-S, CX204Y-24GT-M-S | Multi-rate adaptation; basic security; cost-effective |
Ⅴ. Conclusion
By integrating the three major chip families of Prestera (Falcon, Aldrin 2/3, AlleyCat 5X/5Y) , Teralynx and OCTEON— the hardware core of Marvell Ethernet Switches & Routers — Asterfusion has built a complete network solution covering from access layer, aggregation layer to core layer and intelligent edge. Whether for campus networks, enterprise cores or ultra-large-scale data centers, the combination of Marvell chips and AsterNOS/AsterNOS-VPP can deliver a high-performance, low-latency, programmable and secure network experience.
On this basis, Asterfusion further integrates scattered hardware capabilities into a unified and manageable network system through OpenWiFi Controller, network visualization and automation tools — whether it is dynamic isolation of campus tenants, low-latency transmission of data center GPU clusters, or virtualization offloading of edge nodes, all can be efficiently adapted through the “Marvell chips + AsterNOS” combination.
In the future, with the popularization of 400G/800G ports and the continuous growth of AI computing power demand, Asterfusion will continue to deepen cooperation with Marvell’s open network ASIC architecture, promote technical iterations based on the existing product matrix, and provide enterprises with full-lifecycle network solutions from “hardware selection” to “system deployment” and then to “long-term operation and maintenance”.
